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HPC-SIG: Novel Architecture Focus Group

Cardiff University, 25th April 2008

A meeting of the Novel Architecture Focus Group of the HPC-SIG will be held in the CUBRIC Seminar Room, School of Psychology, Cardiff University commencing 10:45am on 25th April 2008.

The meeting will cover presentations from Novel Architecture suppliers in the UK who provide technical overviews of their offerings and demonstrations of their deployment. These presentations will be driven by application case studies, with user participation in the session, designed to illustrate the effort involved in the development of new codes and migration of existing software focusing throughout on the real performance gains achieved. 

Companies who will be presenting at the meeting include nVIDIA, Clearspeed, Bull and SGI. 

Workshop Agenda:

 Time  Agenda
10:45 - 11:15 Registration (plus refreshments)
11:15 - 11:30 
11:30 - 12:30 Mike Giles (Oxford University)
& JC Baratault (nVIDIA)
12:30 - 13:30 Marc Mendez - Bull (CUDA)
13:30 - 14:00 Buffet Lunch
14:00 - 15:00 Michael Woodacre - SGI (FPGA)
15:00 - 16:00 Simon McIntosh-Smith  - ClearSpeed

& Philip Brown (Bristol University) Presentation to follow
16:00 - 16:30 Nick Avis  - Cardiff: Reconfigurable Computing
16:30 - 17:00 Panel Discussion / Tour of Machine room.
17:00 Close

Presenter and Presentation Abstract:

Company Presenter Title & Abstract
(CUDA) Marc Mendez

Accelerating HPC applications.

While accelerators look like a good idea to add both space and power low-budget processing units to HPC systems, it is foreseen that their integration will require some adjustments so they are made usable to every scientific user:

  • development kits have to improve;
  • resource management may not handle their peculiar properties;
  • most of all, wild parallelism proposed require new algorithms and thoughts. 

Closing up with just announced and future systems aims at opening to further discussions and moving the subject to new scales.

ClearSpeedSimon McIntosh-Smith (ClearSpeed)  
Philip Brown
(Bristol University)

ClearSpeed Acceleration Technology for HPC: From Theory to Practice. 

With the advent of accelerators designed specifically for speeding up 64-bit floating point scientific computing codes, whole new classes of applications can now beneit from the greater performance and increased compute density offered by these solutions. In this presentation we will describe ClearSpeed's accelerator architecture, programming model and product family. In addition we will review the results of three different application ports: one port by ClearSpeed and two by our users.

These application ports will cover:

  1.  The port of the Density Functional Theory component of the Molpro Quantum Chemistry code by Dr. Fred Manby's team;
  2.  The port of the BUDE protein-ligand docking code by Dr. Richard Sessions' team;
  3.  The port of the AMBER molecular dynamics code by ClearSpeed staff.

The description of the Molpro port will be presented by the developer who has been porting the code, Philip Brown from Bristol University.

Oxford UniversityMike GilesGPUs: The next big thing in HPC? In this presentation, I will discuss the very significant potential of GPUs, offering at least 10x better price/performance and energy efficiency than conventional Intel/AMD based systems. Based on my experience with implementing Monte Carlo and finite difference solvers on nVIDIA GPU's using their CUDA development environment, I will also discuss the programming effort required to achieve this potential, and offer my thoughts on what is needed for GPUs to become a mainstream HPC solution.
nVIDIAJC BarataultnVIDIA CUDA software and GPU Parallel Computing Architecture.
SGI (FPGA)Michael WoodacreApplication acceleration and the use of FPGA Technology.
This talk will present an overview of technology available for application acceleration, and provide as an example the development and results obtained accelerating the bioinformatics code, BLAST-N.


If you would like further information on this workshop, please contact us.